Conventionally, there has been a nitride-semiconductor field-effect transistor disclosed in PTL 1 (Japanese Unexamined Patent Application Publication No. 2014-29991). The nitride-semiconductor field-effect transistor includes a nitride semiconductor laminate having a heterointerface. A recess that is recessed toward the heterointerface is provided on a surface of the nitride semiconductor laminate. An insulating film is also provided on the surface of the nitride semiconductor laminate so as to be separated by a predetermined distance from an opening edge of the recess. A drain electrode is formed over a surface of the insulating film from the recess of the nitride semiconductor laminate so as to be in contact with the surface of the nitride semiconductor laminate between the insulating film and the opening edge of the recess.
With such a structure, it is aimed to reduce ON-state maximum electric field strength at an end of the drain electrode adjacent to the nitride semiconductor laminate so that ON withstand voltage is improved.